1. Field of the Disclosure
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to integrated circuits wherein semiconductor-on-insulator techniques are employed.
2. Description of the Related Art
Integrated circuits typically include a large number of integrated circuits, such as field effect transistors. Field effect transistors include a gate structure provided over a channel region, wherein the channel region is provided in a semiconductor material between a source region and a drain region that are doped differently than the channel region.
For improving the performance of integrated circuits including field effect transistors, it has been proposed to employ semiconductor-on-insulator technology. In semiconductor-on-insulator technology, a semiconductor-on-insulator substrate may be provided. The semiconductor-on-insulator substrate includes a thin layer of semiconductor material, for example, silicon, that is provided above a bulk semiconductor material, for example, silicon. The layer of semiconductor material is separated from the bulk semiconductor material by a layer of an electrically insulating material, for example, silicon dioxide. Source, drain and channel regions of field effect transistors may be provided in the layer of semiconductor material. Compared to integrated circuits wherein the source, channel and drain regions of field effect transistors are formed in a bulk semiconductor material, semiconductor-on-insulator technology may allow reducing parasitic capacitances and leakage currents. Moreover, integrated circuits formed in accordance with semiconductor-on-insulator technology may be less sensitive with respect to ionizing radiation.
However, semiconductor-on-insulator technology may have some issues associated therewith, which include the so-called “floating body effect.” The body of a field effect transistor forms a capacitor with the bulk semiconductor material therebelow. In this capacitor, electric charge may accumulate and cause adverse effects, which may include a dependence of the threshold voltage of the field effect transistor on its previous states.
For substantially avoiding the floating body effect, it has been proposed to use fully depleted field effect transistors. Fully depleted field effect transistors are formed using a semiconductor-on-insulator substrate wherein the semiconductor layer provided on the electrically insulating layer has a smaller thickness than a channel depletion width of the field effect transistor. Thus, the electric charge and, accordingly, the body potential of the field effect transistor are fixed.
However, fully depleted field effect transistors may be less suitable for some applications so that it may be desirable to form fully depleted field effect transistors and bulk field effect transistors on a same substrate.
U.S. Pat. No. 8,963,208 discloses removing portions of a semiconductor layer and a dielectric layer from a part of a semiconductor-on-insulator substrate so that a bulk semiconductor material is exposed and performing a selective growth process for depositing a semiconductor material on the bulk semiconductor material, wherein a semiconductor region having a surface that is substantially planar with a surface of a layer of semiconductor material is formed. Thereafter, transistors may be formed both in a portion of the semiconductor-on-insulator substrate wherein the dielectric layer and the semiconductor layer were not removed and on the semiconductor region formed by the selective growth process. However, a selective growth process may significantly contribute to the costs of the manufacturing process.
In view of the situation described above, the present disclosure provides a semiconductor structure and a method for the formation thereof, wherein a selective growth process for forming a bulk semiconductor region having a surface that is substantially planar with a surface of the semiconductor layer of a semiconductor-on-insulator region need not be performed.